1. Field of the Invention
The present invention relates generally to the formation of integrated circuit structures, and more specifically to a technique for forming self-aligned contacts and integrated circuit devices. The technique is particularly adapted for use with very small device geometries.
2. Description of the Prior Art
As feature sizes continue to shrink for semiconductor integrated circuit devices, certain structures become more difficult to perform. One of these is an electrical contact to a substrate, usually made by a polycrystalline silicon interconnect lead. In order to perform contact structures having minimum resistance, it is desirable to make the contact as large as possible. However, continually shrinking sizes make this a goal which is difficult to reach.
Self-aligned structures have been used in the formation of better contacts. However, at continually shrinking device sizes, even self-aligned contacts have problems.
An example of a structure showing the type of problems found even with self-aligned is given in FIG. 1. A substrate 10 contains field oxide regions 12, 14 which define an active region between them. Within the active region, a transistor is formed by a gate electrode 16. The gate electrode 16 includes a gate oxide layer on the surface of a substrate 10, with a doped polycrystalline silicon layer 20 above it. This is all that is required to define a gate electrode, but many structures also contain a silicide layer 22 to improve conductivity, and a cap oxide layer 24 to protect the gate electrode.
Sidewall oxide spacers 26 are formed alongside the electrode 16, and are used in the formation of LDD regions 28. Highly doped source/drain regions 30 are formed outside the LDD regions as is known in the art.
An oxide layer 32 is formed over the entire device, and an opening 34 is formed in it to create a contact to one of the source/drain regions 30. Oxide layer 32 is a conformal oxide layer deposited as known in the art, and is often referred to as an interpoly oxide (IPO) layer. When IPO layer 32 is etched within the opening 34, a sidewall region 36 remains alongside sidewall spacer 26. Sidewall region 36 has a thickness approximately equal to the deposited thickness of IPO layer 32.
Sidewall region 36 causes a smaller surface area to be available for contact to the source/drain region 30. Because the devices are typically made as small as possible, it is not desirable to increase the surface area of the source/drain region 30 to simply provide a more area for the contact. However, it is not realistic to try to remove the sidewall region 36; over etching or use of a wet etch will tend to damage the substrate as well as surrounding oxide regions. Thus, the space available for contact is made smaller by the area taken up by the sidewall region 36.
It would be desirable to provide a processing method, and a resulting structure, which maximize the substrate surface area available for a self-aligned contact. It would further be desirable for a method to produce such structure to be compatible with presently available processing techniques, and to be available without adding to processed complexity.